1. Field of the Invention
The present invention relates to a method of generating an interconnection pattern for a semiconductor integrated circuit or the like.
2. Description of the Prior Art
A conventional automatic interconnection pattern generation system mainly aims at achieving a high integration for a semiconductor device or the like. For this purpose, a functional element, such as a transistor or the like is arranged within every functional circuit block based on logical circuit data or the like, and connections between them are in turn performed by several interconnection layers (layer on photo mask). Furthermore, connections between the functional circuit blocks are also performed by several interconnection layers in a manner similar to that.
Generally, when the functional elements such as a transistor or the like are densely arranged, a circuit area of a semiconductor device or a liquid crystal device will become the smallest area, but as a layout on the interconnection layer, there may still be given room in area between interconnections or the like. And, in a conventional automatic interconnection pattern generation system, only one type of line width data has been prepared for every interconnection layer for each interconnection width, the pattern generation has been made using the interconnection of the prepared line width. However, since an allowable current density for ensuring reliability against such as electromigration has not been taken into consideration in using the interconnection for a long period of time in this method, interconnections with narrow line width have been automatically layouted even at a circuit where a large amount of current has flown, thereby causing harmful effects, such as electromigration, heat generation, or the like. For this reason, a Japanese Laid-Open Patent Application Publication No. 4-107953 discloses a method of changing an interconnection width by means of preparing load current data or the like in advance.
However, in the conventional art described above, although the interconnection width becomes wider in a portion where a large amount of current flows, a pattern generation employing a minimum dimension which has been specified on each interconnection layer in advance is performed in a portion where only a smaller amount of current flows with respect to the allowable current density. Thus, even when there has been still room in area in a portion where this interconnection pattern generation has been performed, there has been a case where a minimum line width has been employed. For the minimum line width, since the pattern width has been narrow, accuracy of interconnection pattern width on photo mask has been required, so that the mask making has been high in cost, resulting in an increase in cost of the semiconductor device or the like. In addition, for the minimum dimension, it has become easy to cause discontinuity and width reduction of the interconnection due to a decrease in a process margin in a photolithography process, resulting in a decrease in yield and quality of the semiconductor or the like.